The invention relates generally to a method for fabricating a semiconductor device and, more specifically, to a technology of forming a floating body transistor used in a highly-integrated semiconductor device using a silicon-on-insulator (SOI) structure.
In many semiconductor device systems, a semiconductor memory apparatus is configured to store data generated or processed in the device. For example, if a request from a data processor such as a central processing unit (CPU) is received, a semiconductor memory apparatus may output data to the data processor from unit cells in the apparatus, or the apparatus may store data processed by the data processor to unit cells of an address transmitted with the request.
As data storage capacities of semiconductor memory apparatus have increased, the sizes of semiconductor memory apparatus have not increased proportionally. Thus, various elements and components used for read or write operations in a semiconductor memory apparatus have also reduced in size. Accordingly, components and elements unnecessarily duplicated in the semiconductor memory apparatus, such as transistors or wires, are combined or merged to decrease the area occupied by each component. Particularly, the reduction of the size of unit cells included in the semiconductor memory apparatus affects improvement of the degree of integration.
As an example of a semiconductor memory apparatus, Dynamic Random Access Memory (DRAM) is a type of volatile memory device configured to retain data while a power source is supplied. The unit cell comprises a transistor and a capacitor. In the case of the unit cell having a capacitor, after the datum “1” is delivered to the capacitor, charges that are temporarily stored in the storage node are dissipated, i.e., the amount of the charge stored therein is reduced, because of both leakage currents generated at junction of the storage nodes and inherent characteristics of the capacitor. As a result, a refresh operation is periodically required on the unit cells so that data stored in the DRAM cannot be destroyed.
In order to prevent the reduction of charge, numerous methods for increasing capacitance (Cs) of the capacitor included in the unit cell have been suggested so that more charges may be stored in the storage node. For example, an insulating film used earlier in the capacitor, e.g., an oxide film, may be replaced with an advanced insulating film which has a larger dielectric constant, such as a nitrified oxide film or a high dielectric film. Otherwise, a capacitor having a two-dimensional structure is changed to have a three-dimensional cylindrical structure or a trench structure, thereby increasing the surface area of both electrodes of the capacitor.
As the design rule is reduced, the plane area where a capacitor can be formed is reduced, and it is difficult to develop materials constituting an insulating film in the capacitor. As a result, the junction resistance value of the storage node (SN) and the turn-on resistance value of the transistor in the unit cell are larger, and accordingly it is difficult to perform normal read and write operations, and refresh characteristics deteriorate.
To improve the above-described shortcomings, the unit cell may comprise a transistor having a floating body. Thus, the unit cell of the semiconductor memory apparatus does not include a capacitor used for storing data, but stores data in a floating body of the transistor included in the unit cell.
In order to store data in the floating body, a voltage level supplied on the word line is reduced by ½ or ⅓ of voltage level applied to the bit line connected to one active region of the transistor, thereby generating hot carriers. When the datum “1” is delivered, a large amount of hot carriers are generated in a junction region of the bit lines (BL). Then, electrons are sent out into the bit line (BL) but holes remain in the floating body (FB). Otherwise, when the datum “0” is transmitted, the hot carriers are not generated in the junction region, so that any holes do not remain in the floating body (FB). The holes kept in the floating body lower the threshold voltage of the transistor of the unit cell; as a result, the amount of current flowing through the transistor increases. That is, the amount of current flowing when the holes are stored in the floating body of the transistor is larger than that flowing when no holes are stored. As a result, it is possible to distinguish whether the datum “1” or “0” is stored in the unit cell.
The semiconductor memory apparatus that comprises the floating body transistor does not include a capacitor, thereby improving the ability to maximize the degree of integration. However, it is difficult to prevent reduction of the amount of holes that the floating body of the FB transistor stores, due to a leakage current that occurs at junctions between the floating body and either a source line or a bit line. Generally, active regions of the transistor, which are connected to the bit line or the source line, include impurities of high concentration in order to reduce resistance resulting from junction with metal layers. However, if the active region (e.g. source or drain region) of the transistor is doped with impurities of high concentration, the amount of leakage current between the active region and the floating body may increase. As a result, the amount of holes stored in the floating body is dissipated as time goes by. Also, since the amount of leakage current increases in proportion to temperature, data stored in the transistor of the unit cell are easily deleted under conditions of high temperature.
FIGS. 1a to 1e are cross-sectional diagrams illustrating a prior art method for manufacturing a floating body transistor in a semiconductor memory apparatus.
Referring to FIG. 1a, a gate oxide film 132 is formed over an upper silicon layer 114 of a silicon-on-insulator (SOI) semiconductor substrate. A gate pattern 120 that comprises a gate electrode including a polysilicon layer 122, a metal layer 124, and a hard mask 116 for protecting the gate electrode is formed. The SOI substrate comprises a lower silicon layer 110, a lower insulating oxide layer 112 formed on the lower silicon layer 110, and an upper silicon layer 114 formed on a lower insulating oxide layer 112. The SOI wafer thus includes an insulating layer 112 that is artificially formed between the upper silicon layer 114, which is the top surface, and the lower silicon layer 110, which is a basic layer, so as to remove the impact from the basic layer, thereby improving the process, efficiency, and characteristics of a high-pure silicon layer formed over the insulating layer. Since the SOI wafer provides a zero-defective thin silicon layer isolated with an insulating layer (thermal oxide film), an insulating wall or a well-forming process is not required, so that the product developing time, producing time, and cost are reduced. Also, there is no burden on equipment investment because the equipment that uses a general wafer reduces unnecessary equipment.
After the gate pattern is formed, an ion implantation process is performed (see the arrows in FIG. 1b) on the upper silicon layer 114 located at both sides of the gate pattern 120, thereby obtaining a source/drain region 130. In order to prevent a hot carrier effect (HCE), the source/drain region 130 is neither deeply formed nor expanded to a lower portion of the gate pattern while the doping concentration is lowered by the ion implantation process.
Referring again to FIG. 1b, a local halo region 140 is formed at a deeper location than the source/drain region 130 in the upper silicon layer 114 through the ion implantation process. The local halo region 140 formed in the body of the transistor is a high concentration doped region that prevents a punch-through phenomenon between the source and the drain. The local halo region 140 prevents the ion-implanted region from diffusing into a space between the source/drain regions by thermal treatment when a plug is formed in a subsequent process.
Referring to FIG. 1c, a spacer 128 is formed at sidewalls of the gate pattern 120, and an oxide film 150 that protects the gate pattern is formed over the sidewalls and the gate pattern. The oxide film, which has been widely used to protect the gate pattern, is formed over the structure including the gate pattern, and a self-aligned etching process is performed on the oxide film to obtain a cap-type oxide film 150 that protects the top surface of the gate pattern. An etch-back process is performed to etch the gate oxide film 132 and the oxide film 150, thereby exposing the source/drain region 130.
Referring to FIG. 1d, a doped polysilicon layer 160 that forms a plug is formed over the structure including the gate pattern 120. The polysilicon layer 160 contacts the gate pattern 120 and the source/drain region 130.
Referring to FIG. 1e, the doped polysilicon layer 160 is diffused into the upper silicon layer 114 by thermal treatment, so that transistors corresponding to each gate pattern 120 are separated, and a source and a drain of each transistor is defined. The diffused polysilicon layer 160a is diffused into the lower insulating oxide layer 112, so that a body of the neighboring transistor is completely isolated.
In the floating body transistor fabricated over the SOI wafer, it is advantageous to isolate cells in a single active region rather than to isolate unit cells through a device isolation film by shallow trench isolation (STI) process in order to maximize the cell packing density. However, when the entire size of the transistor is reduced, the distance between source/drain regions of the transistor having a plane channel region is reduced to cause a punch-through phenomenon, which is difficult to prevent this.
Referring again to FIG. 1e, when the diffusion process is performed at a high temperature after the polysilicon film 160 of high concentration is deposited, the polysilicon film 160 is diffused horizontally as well as vertically, thereby obtaining the diffused polysilicon layer 160a that serves as a plug. Due to the horizontal diffusion, the effective volume of the body of each transistor is reduced (that is, the effective channel length becomes shorter). Also, the punch-through phenomenon may occur in the top or bottom portion of the floating body formed in the upper silicon layer 114.
Specifically, the punch-through phenomenon frequently occurs in the bottom portion of the floating body having a lower concentration than in the top portion of the floating body having a higher concentration by channel doping when the gate pattern 120 is formed. In order to prevent the punch-through phenomenon, an ion tilt implantation process is performed to form the local halo region 140 in the upper silicon layer 114. As the distance between the neighboring gate patterns becomes shorter due to reduction of the design rule, the tilt angle is not sufficiently secured in the ion tilt implantation process, so that it is difficult to form the local halo region 140 in the bottom portion of the floating body. When the local halo region 140 is not formed in the bottom portion of the floating body, it is difficult to prevent the punch-through phenomenon in the floating body of the transistor, thereby degrading the reliability of the device.